At the present time, computers which have been greatly developed are used in various scenes. However, in these Neumann computers, the performance of processing easily made by humans (real-time face recognition or the like) is very low due to their processing system itself.
Regarding this inconvenience, a neural network is studied as an arithmetic processing model in analogy to the brain information processing system.
Generally, in a neural network, a unit corresponding to a neuron inputs products obtained by weighting output values from other plural units (neurons) with synapse weight values, and outputs a value obtained by performing nonlinear conversion on a total sum of the input values.
That is, in a general neural network, summation of products and nonlinear conversion in and among the respective units realize desired processing.
As a neural network architecture using this neuron model, an associated memory where units having a nonlinear input/output characteristic are mutually connected, a pattern recognition model where the units having a nonlinear input/output characteristic are connected in a layer, and the like, have been proposed.
As the neural network is a massively parallel and distributed type information processing model, it is implemented very inefficiently in a sequential-processing type Neumann computer. Accordingly, upon practical use of the neural network, it is necessarily implemented as. a specialized hardware integrated circuit.
Further, upon implementation as an integrated circuit, if an analog arithmetic circuit is employed to realize the above-described summation of products and nonlinear conversion, the number of circuit components is greatly reduced in comparison with a digital arithmetic circuit.
That is, in a case where the summation of products and nonlinear conversion are realized by an analog arithmetic circuit, by functionally utilizing physical characteristics of devices and materials, a desired function can be realized with a greatly smaller number of components in comparison with a digital arithmetic circuit. Various circuits have been proposed as circuits appropriate to the above-described neuron model and neural network architecture.
For example, T. Morie, J. Funakoshi, M. Nagata and A. Iwata propose, in “An Analog-Digital Merged Neural Circuit Using Pulse Width Modulation Technique” (IEICE Trans. Fundamentals, Vol. E82-A, No. 2, pp. 356-363, 1999, http://search.ieice.org/1999/files/e000a02.htm/e82-a,2,356), a system having capacitors corresponding to positive and negative synapse weights to store results of summation for respective signs as electric charges, then to obtain the result of addition between the positive and negative charges by coupling the capacitors.
However, in this system, in a case where the results of parallel arithmetic processing by a large number of analog arithmetic circuits are held with high accuracy, the capacity of the capacitors must be increased. Accordingly, from a viewpoint of area on the chip, further improvement in the performance is desired for reduction of the capacity of the capacitors.
Further, in the system, 2 capacitors must be prepared for respective positive and negative synapse weights. Accordingly, from a viewpoint of area on the chip, further improvement in the performance is desired for reduction of the total capacity of the capacitors.
Further, in a case where a cumulative value is to be calculated using the results of arithmetic computations, it is necessary to hold the results of arithmetic computations for a long time with high accuracy. In this case, there is a problem that the electric charges stored in the capacitors are lost in a short time due to leakage from a pn junction. Accordingly, further improvement in the performance is desired.